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MC9S12XD64MAA Datasheet, PDF (705/1348 Pages) Freescale Semiconductor, Inc – ATD Input Enable Register 0 | |||
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Chapter 19 S12X Debug (S12XDBGV2) Module
Field
3â0
SC[3:0}
Table 19-22. DBGSCR2 Field Descriptions
Description
State Control Bits â These bits select the targeted next state while in State2, based upon the match event.
See Table 19-23.
The trigger priorities described in Table 19-38 dictate that in the case of simultaneous matches, the match on
the lower channel number ([0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to ï¬nal
state has priority over all other matches.
SC[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Table 19-23. State2 Sequencer Next State Selection
Description
Any match triggers to state1
Any match triggers to state3
Any match triggers to ï¬nal state
Match3 triggers to State1....... Other matches have no effect
Match3 triggers to State3....... Other matches have no effect
Match3 triggers to ï¬nal state....... Other matches have no effect
Match0 triggers to State1....... Match1 triggers to State3....... Other matches have no effect
Match1 triggers to State3....... Match0 triggers ï¬nal state....... Other matches have no effect
Match0 triggers to State1....... Match2 triggers to State3....... Other matches have no effect
Match2 triggers to State3....... Match0 triggers ï¬nal state....... Other matches have no effect
Match1 triggers to State1....... Match3 triggers to State3....... Other matches have no effect
Match3 triggers to State3....... Match1 triggers ï¬nal state....... Other matches have no effect
Reserved
Reserved
Reserved
Reserved
19.3.1.10 Debug State Control Register 3 (DBGSCR3)
0x0027
7
6
5
4
R
0
0
0
0
W
Reset
0
0
0
0
Unimplemented or Reserved
3
SC3
0
2
SC2
0
1
SC1
0
0
SC0
0
Figure 19-12. Debug State Control Register 3 (DBGSCR3)
Read: Anytime
Write: Anytime when DBG not armed.
This register is visible at 0x0027 only with COMRV[1]=1. The state control register 3 selects the targeted
next state while in State3. The matches refer to the match channels of the comparator match control logic
as depicted in Figure 19-1 and described in Section 19.3.1.11.1, âDebug Comparator Control Register
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
707
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