|
MC9S12XD64MAA Datasheet, PDF (37/1348 Pages) Freescale Semiconductor, Inc – ATD Input Enable Register 0 | |||
|
◁ |
Chapter 1 Device Overview MC9S12XD-Family
1.1.4 Device Memory Map
Table 1-1shows the device register memory map of the MC9S12XDP512. Available modules on other
Family members please refer to Appendix E Derivative Differences
Unimplemented register space shown in Table 1-1 is not allocated to any module. Writing to these
locations have no effect. Read access to these locations returns zero. Figure 1-1 shows the global address
mapping for the parts listed in Table 1-2.
Table 1-1. Device Register Memory Map
Address
0x0000â0x0009
0x000Aâ0x000B
0x000Câ0x000D
0x000Eâ0x000F
0x0010â0x0017
0x0018â0x0019
0x001Aâ0x001B
0x001Câ0x001F
0x0020â0x002F
0x0030â0x0031
0x0032â0x0033
0x0034â0x003F
0x0040â0x007F
0x0080â0x00AF
0x00B0â0x00B7
0x00B8â0x00C7
0x00B8â0x00BF
0x00C0â0x00C7
0x00C8â0x00CF
0x00D0â0x00D7
0x00D8â0x00DF
0x00E0â0x00E7
0x00E8â0x00EF
0x00F0â0x00F7
0x00F8â0x013F
0x00F8â0x00FF
0x0100â0x010F
Module
Size
(Bytes)
PIM (port integration module)
10
MMC (memory map control)
2
PIM (port integration module)
2
EBI (external bus interface)
2
MMC (memory map control)
8
Unimplemented
2
Device ID register
2
PIM (port integration module)
4
DBG (debug module)
16
MMC (memory map control)
2
PIM (port integration module)
2
CRG (clock and reset generator)
12
ECT (enhanced capture timer 16-bit 8-channel)s
64
ATD1 (analog-to-digital converter 10-bit 16-channel) 48
IIC1 (inter IC bus)
8
Reserved
16
SCI2 (serial communications interface)
8
SCI3 (serial communications interface)
8
SCI0 (serial communications interface)
8
SCI1 (serial communications interface)
8
SPI0 (serial peripheral interface)
8
IIC0 (inter IC bus)
8
Unimplemented
8
SPI1 (serial peripheral interface)
8
Reserved
8
SPI2 (serial peripheral interface)
8
Flash control register
16
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
37
|
▷ |