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MC9S12XD64MAA Datasheet, PDF (438/1348 Pages) Freescale Semiconductor, Inc – ATD Input Enable Register 0 | |||
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Chapter 10 Freescaleâs Scalable Controller Area Network (S12MSCANV3)
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1), except bits IDHITx, which are
read-only
Table 10-16. CANIDAC Register Field Descriptions
Field
Description
5:4
Identiï¬er Acceptance Mode â The CPU sets these ï¬ags to deï¬ne the identiï¬er acceptance ï¬lter organization
IDAM[1:0] (see Section 10.4.3, âIdentiï¬er Acceptance Filterâ). Table 10-17 summarizes the different settings. In ï¬lter closed
mode, no message is accepted such that the foreground buffer is never reloaded.
2:0
Identiï¬er Acceptance Hit Indicator â The MSCAN sets these ï¬ags to indicate an identiï¬er acceptance hit (see
IDHIT[2:0] Section 10.4.3, âIdentiï¬er Acceptance Filterâ). Table 10-18 summarizes the different settings.
IDAM1
0
0
1
1
Table 10-17. Identiï¬er Acceptance Mode Settings
IDAM0
0
1
0
1
Identiï¬er Acceptance Mode
Two 32-bit acceptance ï¬lters
Four 16-bit acceptance ï¬lters
Eight 8-bit acceptance ï¬lters
Filter closed
Table 10-18. Identiï¬er Acceptance Hit Indication
IDHIT2
IDHIT1
IDHIT0
Identiï¬er Acceptance Hit
0
0
0
Filter 0 hit
0
0
1
0
1
0
0
1
1
Filter 1 hit
Filter 2 hit
Filter 3 hit
1
0
0
1
0
1
1
1
0
Filter 4 hit
Filter 5 hit
Filter 6 hit
1
1
1
Filter 7 hit
The IDHITx indicators are always related to the message in the foreground buffer (RxFG). When a
message gets shifted into the foreground buffer of the receiver FIFO the indicators are updated as well.
10.3.2.13 MSCAN Reserved Register
This register is reserved for factory testing of the MSCAN module and is not available in normal system
operation modes.
MC9S12XDP512 Data Sheet, Rev. 2.21
438
Freescale Semiconductor
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