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MC9S12XD64MAA Datasheet, PDF (389/1348 Pages) Freescale Semiconductor, Inc – ATD Input Enable Register 0 | |||
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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1)
To calculate the output frequency in center aligned output mode for a particular channel, take the selected
clock source frequency for the channel (A, B, SA, or SB) and divide it by twice the value in the period
register for that channel.
⢠PWMx Frequency = Clock (A, B, SA, or SB) / (2*PWMPERx)
⢠PWMx Duty Cycle (high time as a% of period):
â Polarity = 0 (PPOLx = 0)
Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100%
â Polarity = 1 (PPOLx = 1)
Duty Cycle = [PWMDTYx / PWMPERx] * 100%
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
389
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