MC9S12XD64MAA Datasheet, PDF (197/1348 Pages) Freescale Semiconductor, Inc – ATD Input Enable Register 0

Chapter 6 XGATE (S12XGATEV2)
6.3.1.7 XGATE Condition Code Register (XGCCR)
The XGCCR register (Figure 6-9) provides access to the RISC core’s condition code register.
7
6
5
4
R
0
0
0
0
W
Reset
0
0
0
0
= Unimplemented or Reserved
3
XGN
0
2
XGZ
0
1
XGV
0
Figure 6-9. XGATE Condition Code Register (XGCCR)
Read: In debug mode if unsecured
Write: In debug mode if unsecured
Table 6-7. XGCCR Field Descriptions
Field
3
XGN
2
XGZ
1
XGV
0
XGC
Sign Flag — The RISC core’s Sign flag
Description
Zero Flag — The RISC core’s Zero flag
Overflow Flag — The RISC core’s Overflow flag
Carry Flag — The RISC core’s Carry flag
0
XGC
0
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
197