MC9S12XD64MAA Datasheet, PDF (534/1348 Pages) Freescale Semiconductor, Inc – ATD Input Enable Register 0

Chapter 12 Serial Peripheral Interface (S12SPIV4)
End of Idle State
SCK Edge Number
SCK (CPOL = 0)
Begin
Transfer
End
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Begin of Idle State
SCK (CPOL = 1)
SAMPLE I
MOSI/MISO
CHANGE O
MOSI pin
CHANGE O
MISO pin
SEL SS (O)
Master only
SEL SS (I)
t_L
t_T t_I t_L
MSB first (LSBFE = 0): MSB
LSB first (LSBFE = 1): LSB
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
LSB Minimum 1/2 SCK
MSB
for t_T, t_l, t_L
t_L = Minimum leading time before the first SCK edge, not required for back-to-back transfers
t_T = Minimum trailing time after the last SCK edge
t_I = Minimum idling time between transfers (minimum SS high time), not required for back-to-back transfers
Figure 12-12. SPI Clock Format 1 (CPHA = 1)
The SS line can remain active low between successive transfers (can be tied low at all times). This format
is sometimes preferred in systems having a single fixed master and a single slave that drive the MISO data
line.
• Back-to-back transfers in master mode
In master mode, if a transmission has completed and a new data byte is available in the SPI data
register, this byte is sent out immediately without a trailing and minimum idle time.
The SPI interrupt request flag (SPIF) is common to both the master and slave modes. SPIF gets set one
half SCK cycle after the last SCK edge.
MC9S12XDP512 Data Sheet, Rev. 2.21
534
Freescale Semiconductor