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MC9S12XD64MAA Datasheet, PDF (338/1348 Pages) Freescale Semiconductor, Inc – ATD Input Enable Register 0 | |||
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
Table 7-23. Modulus Counter Prescaler Select
MCPR1
0
0
1
1
MCPR0
0
1
0
1
Prescaler Division
1
4
8
16
7.3.2.20 16-Bit Modulus Down-Counter FLAG Register (MCFLG)
R
W
Reset
7
6
5
4
3
2
1
0
0
0
POLF3
POLF2
POLF1
MCZF
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-42. 16-Bit Modulus Down-Counter FLAG Register (MCFLG)
0
POLF0
0
Read: Anytime
Write only used in the ï¬ag clearing mechanism for bit 7. Writing a one to bit 7 clears the ï¬ag. Writing a
zero will not affect the current status of the bit.
NOTE
When TFFCA = 1, the ï¬ag cannot be cleared via the normal ï¬ag clearing
mechanism (writing a one to the ï¬ag). Reference Section 7.3.2.6, âTimer
System Control Register 1 (TSCR1)â.
All bits reset to zero.
Table 7-24. MCFLG Field Descriptions
Field
Description
7
MCZF
Modulus Counter Underï¬ow Flag â The ï¬ag is set when the modulus down-counter reaches 0x0000.
The ï¬ag indicates when interrupt conditions have occurred. The ï¬ag can be cleared via the normal ï¬ag clearing
mechanism (writing a one to the ï¬ag) or via the fast ï¬ag clearing mechanism (Reference TFFCA bit in
Section 7.3.2.6, âTimer System Control Register 1 (TSCR1)â).
3:0
POLF[3:0]
First Input Capture Polarity Status â These are read only bits. Writes to these bits have no effect.
Each status bit gives the polarity of the ï¬rst edge which has caused an input capture to occur after capture latch
has been read.
Each POLFx corresponds to a timer PORTx input.
0 The ï¬rst input capture has been caused by a falling edge.
1 The ï¬rst input capture has been caused by a rising edge.
MC9S12XDP512 Data Sheet, Rev. 2.21
338
Freescale Semiconductor
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