MC68HC908GR16 Datasheet, PDF (80/276 Pages) Motorola, Inc – Microcontrollers

Configuration Register (CONFIG)
Address:
Read:
Write:
Reset:
$001E
Bit 7
6
5
4
3
2
1
0
0
0
0
R
TMBCLK- OSCEN-
SEL INSTOP
0
0
0
0
0
0
0
= Unimplemented
R
= Reserved
Figure 5-1. Configuration Register 2 (CONFIG2)
Bit 0
ESCIBD-
SRC
1
Address: $001F
Bit 7
6
5
4
Read:
COPRS LVISTOP LVIRSTD LVIPWRD
Write:
Reset: 0
0
0
0
Note: LVI5OR3 bit is only reset via POR (power-on reset)
3
LVI5OR3
See note
2
SSREC
0
1
STOP
0
Figure 5-2. Configuration Register 1 (CONFIG1)
Bit 0
COPD
0
TMBCLKSEL— Timebase Clock Select Bit
TMBCLKSEL enables an extra divide-by-128 prescaler in the timebase module. Setting this bit enables
the extra prescaler and clearing this bit disables it. See Chapter 4 Clock Generator Module (CGM) for
a more detailed description of the external clock operation.
1 = Enables extra divide-by-128 prescaler in timebase module
0 = Disables extra divide-by-128 prescaler in timebase module
OSCENINSTOP — Oscillator Enable In Stop Mode Bit
OSCENINSTOP, when set, will enable oscillator to continue to generate clocks in stop mode. See
Chapter 4 Clock Generator Module (CGM). This function is used to keep the timebase running while
the reset of the MCU stops. See Chapter 17 Timebase Module (TBM). When clear, oscillator will cease
to generate clocks while in stop mode. The default state for this option is clear, disabling the oscillator
in stop mode.
1 = Oscillator enabled to operate during stop mode
0 = Oscillator disabled during stop mode (default)
ESCIBDSRC — SCI Baud Rate Clock Source Bit
ESCIBDSRC controls the clock source used for the serial communications interface (SCI). The setting
of this bit affects the frequency at which the SCI operates.See Chapter 14 Enhanced Serial
Communications Interface (ESCI) Module.
1 = Internal data bus clock used as clock source for SCI (default)
0 = External oscillator used as clock source for SCI
COPRS — COP Rate Select Bit
COPD selects the COP timeout period. Reset clears COPRS. See Chapter 6 Computer Operating
Properly (COP) Module
1 = COP timeout period = 8176 CGMXCLK cycles
0 = COP timeout period = 262,128 CGMXCLK cycles
LVISTOP — LVI Enable in Stop Mode Bit
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode.
Reset clears LVISTOP.
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
MC68HC908GR16 Data Sheet, Rev. 5.0
80
Freescale Semiconductor