MC68HC908GR16 Datasheet, PDF (208/276 Pages) Motorola, Inc – Microcontrollers

Serial Peripheral Interface (SPI) Module
SPTE SPTIE SPE
NOT AVAILABLE
SPI TRANSMITTER
CPU INTERRUPT REQUEST
SPRIE SPRF
NOT AVAILABLE
ERRIE
MODF
OVRF
SPI RECEIVER/ERROR
CPU INTERRUPT REQUEST
Figure 16-12. SPI Interrupt Request Generation
16.9 Resetting the SPI
Any system reset completely resets the SPI. Partial resets occur whenever the SPI enable bit (SPE) is
low. Whenever SPE is low, the following occurs:
• The SPTE flag is set.
• Any transmission currently in progress is aborted.
• The shift register is cleared.
• The SPI state counter is cleared, making it ready for a new complete transmission.
• All the SPI port logic is defaulted back to being general-purpose I/O.
These items are reset only by a system reset:
• All control bits in the SPCR register
• All control bits in the SPSCR register (MODFEN, ERRIE, SPR1, and SPR0)
• The status flags SPRF, OVRF, and MODF
By not resetting the control bits when SPE is low, the user can clear SPE between transmissions without
having to set all control bits again when SPE is set back high for the next transmission.
By not resetting the SPRF, OVRF, and MODF flags, the user can still service these interrupts after the
SPI has been disabled. The user can disable the SPI by writing 0 to the SPE bit. The SPI can also be
disabled by a mode fault occurring in an SPI that was configured as a master with the MODFEN bit set.
16.10 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
MC68HC908GR16 Data Sheet, Rev. 5.0
208
Freescale Semiconductor