MC68HC908GR16 Datasheet, PDF (242/276 Pages) Motorola, Inc – Microcontrollers

Development Support
19.3 Monitor ROM (MON)
This section describes the monitor ROM (MON) and the monitor mode entry methods. The monitor ROM
allows complete testing of the microcontroller unit (MCU) through a single-wire interface with a host
computer. Monitor mode entry can be achieved without use of the higher test voltage, V_TST, as long as
vector addresses $FFFE and $FFFF are blank, thus reducing the hardware requirements for in-circuit
programming.
Features of the monitor ROM include:
• Normal user-mode pin functionality
• One pin dedicated to serial communication between monitor read-only memory (ROM) and host
computer
• Standard mark/space non-return-to-zero (NRZ) communication with host computer
• Standard communication baud rate (9,600 @ 2.4576-MHz bus frequency)
• Execution of code in random-access memory (RAM) or FLASH
• FLASH memory security feature⁽¹⁾
• FLASH memory programming interface
• 350 bytes monitor ROM code size ($FE20 to $FF6A)
• Monitor mode entry without high voltage, V_TST, if reset vector is blank ($FFFE and $FFFF contain
$FF)
• Normal monitor mode entry if high voltage is applied to IRQ
19.3.1 Functional Description
Figure 19-9 shows a simplified diagram of the monitor mode.
The monitor ROM receives and executes commands from a host computer.
Figure 19-10 and Figure 19-11 show example circuits used to enter monitor mode and communicate with
a host computer via a standard RS-232 interface.
Simple monitor commands can access any memory address. In monitor mode, the MCU can execute
code downloaded into RAM by a host computer while most MCU pins retain normal operating mode
functions. All communication between the host computer and the MCU is through the PTA0 pin. A
level-shifting and multiplexing interface is required between PTA0 and the host computer. PTA0 is used
in a wired-OR configuration and requires a pullup resistor.
Table 19-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode
may be entered after a power-on reset (POR) and will allow communication at 14,400 baud provided one
of the following sets of conditions is met:
• If $FFFE and $FFFF does not contain $FF (programmed state):
– The external clock is 4.9152 MHz
– PTB4 = low
– IRQ = V_TST
• If $FFFE and $FFFF do not contain $FF (programmed state):
– The external clock is 9.8304 MHz
– PTB4 = high
– IRQ = V_TST
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult
for unauthorized users.
MC68HC908GR16 Data Sheet, Rev. 5.0
242
Freescale Semiconductor