MC68HC908GR16 Datasheet, PDF (189/276 Pages) Motorola, Inc – Microcontrollers

Exception Control
Interrupt Status Register 2
Address: $FE05
Bit 7
6
5
4
3
2
Read: I14
I13
I12
I11
I10
I9
Write: R
R
R
R
R
R
Reset: 0
0
0
0
0
0
R
= Reserved
1
Bit 0
I8
I7
R
R
0
0
Figure 15-14. Interrupt Status Register 2 (INT2)
I14–I7 — Interrupt Flags 14–7
These flags indicate the presence of interrupt requests from the sources shown in Table 15-3.
1 = Interrupt request present
0 = No interrupt request present
Interrupt Status Register 3
Address: $FE06
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
I20
I19
I18
I17
I16
I15
Write: R
R
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
0
0
R
= Reserved
Figure 15-15. Interrupt Status Register 3 (INT3)
Bits 7–6 — Always read 0
I20–I15 — Interrupt Flags 20–15
These flags indicate the presence of an interrupt request from the source shown in Table 15-3.
1 = Interrupt request present
0 = No interrupt request present
15.5.2 Reset
All reset sources always have equal and highest priority and cannot be arbitrated.
15.5.3 Break Interrupts
The break module can stop normal program flow at a software-programmable break point by asserting its
break interrupt output (see Chapter 18 Timer Interface Module (TIM)). The SIM puts the CPU into the
break state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module
to see how each module is affected by the break state.
15.5.4 Status Flag Protection in Break Mode
The SIM controls whether status flags contained in other modules can be cleared during break mode. The
user can select whether flags are protected from being cleared by properly initializing the break clear flag
enable bit (BCFE) in the SIM break flag control register (SBFCR).
Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This
protection allows registers to be freely read and written during break mode without losing status flag
information.
MC68HC908GR16 Data Sheet, Rev. 5.0
Freescale Semiconductor
189