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MC68HC908GR16 Datasheet, PDF (258/276 Pages) Motorola, Inc – Microcontrollers
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Electrical Specifications
Characteristic(1)
Monitor mode entry voltage
Low-voltage inhibit, trip falling voltage
Low-voltage inhibit, trip rising voltage
Low-voltage inhibit reset/recover hysteresis
(VTRIPF + VHYS = VTRIPR)
POR rearm voltage(8)
POR reset voltage(9)
POR rise time ramp rate(10)
Symbol
VTST
VTRIPF
VTRIPR
VHYS
VPOR
VPORRST
RPOR
Min
VDD + 2.5
2.35
2.4
—
0
0
0.035
Typ(2)
—
2.6
2.66
100
—
700
—
Max
VDD + 4.0
2.7
2.8
—
100
800
—
Unit
V
V
V
mV
mV
mV
V/ms
1. VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = TA (min) to TA (max), unless otherwise noted
2. Typical values reflect average measurements at midpoint of voltage range, 25°C only.
3. Run (operating) IDD measured using external square wave clock source (fOSC = 16 MHz). All inputs 0.2 V from rail. No dc
loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
affects run IDD. Measured with all modules enabled.
4. Wait IDD measured using external square wave clock source (fOSC = 16 MHz). All inputs 0.2 V from rail. No dc loads. Less
than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait IDD.
Measured with CGM and LVI enabled.
5. Stop IDD is measured with OSC1 = VSS.
6. Stop IDD with TBM enabled is measured using an external square wave clock source (fOSC = 16 MHz). All inputs 0.2 V from
rail. No dc loads. Less than 100 pF on all outputs. All inputs configured as inputs.
7. Pullups and pulldowns are disabled.
8. Maximum is highest voltage that POR is guaranteed.
9. Maximum is highest voltage that POR is possible.
10. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum
VDD is reached.
MC68HC908GR16 Data Sheet, Rev. 5.0
258
Freescale Semiconductor
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