MC68HC908GR16 Datasheet, PDF (34/276 Pages) Motorola, Inc – Microcontrollers

Memory
Addr.
Register Name
$0035
Timer 2 Channel 1 ^Read:
Register Low (T2CH1L) Write:
See page 236. _Reset:
$0036
PLL Control Register ^Read:
(PCTL) Write:
See page 70. _Reset:
$0037
PLL Bandwidth Control ^Read:
Register (PBWC) Write:
See page 72. _Reset:
$0038
PLL Multiplier Select High ^Read:
Register (PMSH) Write:
See page 73. _Reset:
$0039
PLL Multiplier Select Low ^Read:
Register (PMSL) Write:
See page 73. _Reset:
$003A
PLL VCO Select Range ^Read:
Register (PMRS) Write:
See page 74. _Reset:
$003B
PLL Reference Divider ^Read:
Select Register (PMDS) Write:
See page 74. _Reset:
$003C
ADC Status and Control ^Read:
Register (ADSCR) Write:
See page 53. _Reset:
$003D
ADC Data High Register ^Read:
(ADRH) Write:
See page 55. _Reset:
$003E
ADC Data Low Register ^Read:
(ADRL) Write:
See page 55. _Reset:
$003F
ADC Clock Register ^Read:
(ADCLK) Write:
See page 57. _Reset:
$FE00
Break Status Register ^Read:
(BSR) Write:
See page 241. _Reset:
2. Writing a 0 clears SBSW.
Bit 7
Bit 7
PLLIE
0
AUTO
0
0
0
MUL7
0
VRS7
0
0
0
COCO
R
0
0
AD7
ADIV2
0
R
0
6
6
PLLF
0
LOCK
0
0
0
MUL6
1
VRS6
1
0
0
AIEN
0
0
AD6
ADIV1
0
R
0
5
4
3
2
5
4
3
2
Indeterminate after reset
PLLON
BCS
PRE1
PRE0
1
0
0
0
0
0
0
ACQ
0
0
0
0
0
0
MUL11 MUL10
0
0
0
0
MUL5
MUL4
MUL3
MUL2
0
0
0
0
VRS5
VRS4
VRS3
VRS2
0
0
0
0
0
0
RDS3
RDS2
0
0
0
0
ADCO ADCH4 ADCH3 ADCH2
0
1
1
1
0
0
0
0
1
1
VPR1
0
0
0
MUL9
0
MUL1
0
VRS1
0
RDS1
0
ADCH1
1
AD9
Bit 0
Bit 0
VPR0
0
R
0
MUL8
0
MUL0
0
VRS0
0
RDS0
1
ADCH0
1
AD9
Unaffected by reset
AD5
AD4
A3
AD2
AD1
AD0
Unaffected by reset
0
ADIV0 ADICLK MODE1 MODE0
R
0
0
0
1
0
0
SBSW
R
R
R
R
R
(Note 2)
0
0
0
0
0
0
= Unimplemented
R = Reserved U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 8)
MC68HC908GR16 Data Sheet, Rev. 5.0
34
Freescale Semiconductor