MC68HC908GR16 Datasheet, PDF (132/276 Pages) Motorola, Inc – Microcontrollers

Input/Output Ports (PORTS)
When bit DDRDx is a 1, reading address $0003 reads the PTDx data latch. When bit DDRDx is a 0,
reading address $0003 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 12-5 summarizes the operation of the port D pins.
Table 12-5. Port D Pin Functions
PTDPUE
Bit
1
0
X
DDRD
Bit
0
0
1
PTD
Bit
X⁽¹⁾
X
X
I/O Pin
Mode
Input, V_DD(2)
Input, Hi-Z⁽⁴⁾
Output
Accesses to DDRD
Read/Write
DDRD7–DDRD0
DDRD7–DDRD0
DDRD7–DDRD0
1. X = Don’t care
2. I/O pin pulled up to V_DD by internal pullup device.
3. Writing affects data register, but does not affect input.
4. Hi-Z = High imp[edance
Accesses to PTD
Read
Write
Pin
PTD7–PTD0⁽³⁾
Pin
PTD7–PTD0⁽³⁾
PTD7–PTD0
PTD7–PTD0
12.5.3 Port D Input Pullup Enable Register
The port D input pullup enable register (PTDPUE) contains a software configurable pullup device for each
of the eight port D pins. Each bit is individually configurable and requires that the data direction register,
DDRD, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port
bit’s DDRD is configured for output mode.
Address: $000F
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PTDPUE7 PTDPUE6 PTDPUE5 PTDPUE4 PTDPUE3 PTDPUE2 PTDPUE1 PTDPUE0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 12-16. Port D Input Pullup Enable Register (PTDPUE)
PTDPUE7–PTDPUE0 — Port D Input Pullup Enable Bits
These writable bits are software programmable to enable pullup devices on an input port bit.
1 = Corresponding port D pin configured to have internal pullup
0 = Corresponding port D pin has internal pullup disconnected
MC68HC908GR16 Data Sheet, Rev. 5.0
132
Freescale Semiconductor