MC68HC908GR16 Datasheet, PDF (219/276 Pages) Motorola, Inc – Microcontrollers

Table 17-1. Timebase Divider Selection
TBR2
0
0
0
0
1
1
1
1
TBR1
0
0
1
1
0
0
1
1
TBR0
0
1
0
1
0
1
0
1
Divider Tap
TMBCLKSEL
0
1
32,768
4,194,304
8192
1,048,576
2048
262144
128
16,384
64
8192
32
4096
16
2048
8
1024
Low-Power Modes
As an example, a clock source of 4.9152 MHz, with the TMBCLKSEL set for divide-by-128 and the
TBR2–TBR0 set to {011}, the divider tap is1 and the interrupt rate calculates to:
1/(4.9152 x 10⁶/128) = 26 μs
NOTE
Do not change TBR2–TBR0 bits while the timebase is enabled (TBON = 1).
17.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
17.6.1 Wait Mode
The timebase module remains active after execution of the WAIT instruction. In wait mode the timebase
register is not accessible by the CPU.
If the timebase functions are not required during wait mode, reduce the power consumption by stopping
the timebase before executing the WAIT instruction.
17.6.2 Stop Mode
The timebase module may remain active after execution of the STOP instruction if the internal clock
generator has been enabled to operate during stop mode through the OSCENINSTOP bit in the
configuration register. The timebase module can be used in this mode to generate a periodic wakeup from
stop mode.
If the internal clock generator has not been enabled to operate in stop mode, the timebase module will
not be active during stop mode. In stop mode, the timebase register is not accessible by the CPU.
If the timebase functions are not required during stop mode, reduce power consumption by disabling the
timebase module before executing the STOP instruction.
MC68HC908GR16 Data Sheet, Rev. 5.0
Freescale Semiconductor
219