MC68HC908GR16 Datasheet, PDF (55/276 Pages) Motorola, Inc – Microcontrollers

3.8.2 ADC Data Register High and Data Register Low
I/O Registers
3.8.2.1 Left Justified Mode
In left justified mode, the ADRH register holds the eight MSBs of the 10-bit result. The ADRL register holds
the two LSBs of the 10-bit result. All other bits read as 0. ADRH and ADRL are updated each time an ADC
single channel conversion completes. Reading ADRH latches the contents of ADRL until ADRL is read.
All subsequent results will be lost until the ADRH and ADRL reads are completed.
Address: $003D
ADRH
Bit 7
6
5
4
3
2
1
Bit 0
Read: AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
Write:
Reset:
Unaffected by reset
Address: $003E
ADRL
Read: AD1
AD0
0
0
0
0
0
0
Write:
Reset:
Unaffected by reset
= Unimplemented
Figure 3-5. ADC Data Register High (ADRH) and Low (ADRL)
3.8.2.2 Right Justified Mode
In right justified mode, the ADRH register holds the two MSBs of the
10-bit result. All other bits read as 0. The ADRL register holds the eight LSBs of the 10-bit result. ADRH
and ADRL are updated each time an ADC single channel conversion completes. Reading ADRH latches
the contents of ADRL until ADRL is read. All subsequent results will be lost until the ADRH and ADRL
reads are completed.
Address: $003D
ADRH
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
0
0
0
AD9
AD8
Write:
Reset:
Unaffected by reset
Address: $003E
ADRL
Read: AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Write:
Reset:
Unaffected by reset
= Unimplemented
Figure 3-6. ADC Data Register High (ADRH) and Low (ADRL)
MC68HC908GR16 Data Sheet, Rev. 5.0
Freescale Semiconductor
55