MC68HC908GR16 Datasheet, PDF (179/276 Pages) Motorola, Inc – Microcontrollers

STOP/WAIT
CONTROL
SIM
COUNTER
SIM Bus Clock Control and Generation
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO CGM)
CGMXCLK (FROM CGM)
CGMOUT (FROM CGM)
÷2
RESET
PIN LOGIC
V_DD
INTERNAL
PULLUP
DEVICE
CLOCK
CONTROL
CLOCK GENERATORS
POR CONTROL
RESET PIN CONTROL
SIM RESET STATUS REGISTER
MASTER
RESET
CONTROL
RESET
INTERNAL CLOCKS
FORCED MONITOR MODE ENTRY
LVI (FROM LVI MODULE)
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP (FROM COP MODULE)
INTERRUPT CONTROL
AND PRIORITY DECODE
Figure 15-2. SIM Block Diagram
INTERRUPT SOURCES
CPU INTERFACE
15.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 15-4. This clock
originates from either an external oscillator or from the on-chip PLL.
15.2.1 Bus Timing
In user mode, the internal bus frequency is either the crystal oscillator output (CGMXCLK) divided by four
or the PLL output (CGMVCLK) divided by four.
15.2.2 Clock Startup from POR or LVI Reset
When the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the
CPU and peripherals are inactive and held in an inactive phase until after the 4096 CGMXCLK cycle POR
timeout has completed. The RST pin is driven low by the SIM during this entire period. The IBUS clocks
start upon completion of the timeout.
MC68HC908GR16 Data Sheet, Rev. 5.0
Freescale Semiconductor
179