MC68HC908GR16 Datasheet, PDF (150/276 Pages) Motorola, Inc – Microcontrollers

Enhanced Serial Communications Interface (ESCI) Module
The baud rate clock source for the ESCI can be selected via the configuration bit, ESCIBDSRC, of the
CONFIG2 register ($001E).
For reference, a summary of the ESCI module input/output registers is provided in Figure 14-3.
Addr.
$0009
$000A
$000B
$0013
$0014
$0015
$0016
$0017
$0018
$0019
Register Name
ESCI Prescaler Register ^Read:
(SCPSC) Write:
See page 170. _Reset:
ESCI Arbiter Control ^Read:
Register (SCIACTL) Write:
See page 174. _Reset:
ESCI Arbiter Data ^Read:
Register (SCIADAT) Write:
See page 175. _Reset:
ESCI Control Register 1 ^Read:
(SCC1) Write:
See page 161. _Reset:
ESCI Control Register 2 ^Read:
(SCC2) Write:
See page 163. _Reset:
ESCI Control Register 3 ^Read:
(SCC3) Write:
See page 164. _Reset:
ESCI Status Register 1 ^Read:
(SCS1) Write:
See page 165. _Reset:
ESCI Status Register 2 ^Read:
(SCS2) Write:
See page 168. _Reset:
ESCI Data Register ^Read:
(SCDR) Write:
See page 168. _Reset:
ESCI Baud Rate Register ^Read:
(SCBR) Write:
See page 169. _Reset:
Bit 7
PDS2
0
AM1
0
ARD7
0
LOOPS
0
SCTIE
0
R8
U
SCTE
1
0
0
R7
T7
LINT
0
6
PDS1
0
ALOST
0
ARD6
5
PDS0
0
AM0
0
ARD5
0
ENSCI
0
TCIE
0
T8
0
TC
0
TXINV
0
SCRIE
0
R
0
SCRF
1
0
0
0
0
0
R6
R5
T6
T5
LINR
SCP1
0
0
= Unimplemented
4
PSSB4
0
ACLK
0
ARD4
3
PSSB3
0
AFIN
0
ARD3
2
PSSB2
0
ARUN
0
ARD2
0
0
0
M
WAKE
ILTY
0
0
0
ILIE
TE
RE
0
0
0
R
ORIE
NEIE
0
0
0
IDLE
OR
NF
0
0
0
0
0
0
0
0
0
R4
R3
R2
T4
T3
T2
Unaffected by reset
SCP0
R
SCR2
0
0
0
R = Reserved
Figure 14-3. ESCI I/O Register Summary
1
PSSB1
0
AROVFL
0
ARD1
0
PEN
0
RWU
0
FEIE
0
FE
0
BKF
0
R1
T1
SCR1
0
Bit 0
PSSB0
0
ARD8
0
ARD0
0
PTY
0
SBK
0
PEIE
0
PE
0
RPF
0
R0
T0
SCR0
0
14.4.1 Data Format
The SCI uses the standard non-return-to-zero mark/space data format illustrated in Figure 14-4.
MC68HC908GR16 Data Sheet, Rev. 5.0
150
Freescale Semiconductor