MC68HC908GR16 Datasheet, PDF (259/276 Pages) Motorola, Inc – Microcontrollers

5.0-Volt Control Timing
20.7 5.0-Volt Control Timing
Characteristic⁽¹⁾
Symbol
Min
Max
Unit
Frequency of operation
Crystal option
External clock option⁽²⁾
f_OSC
32
100
kHz
dc
32.8
MHz
Internal operating frequency
Internal clock period (1/f_OP)
RESET input pulse width low⁽³⁾
IRQ interrupt pulse width low⁽⁴⁾ (edge-triggered)
IRQ interrupt pulse period
f_OP (f_Bus)
t_CYC
t_IRL
t_ILIH
t_ILIL
—
122
50
50
Note 5
8.2
MHz
—
ns
—
ns
—
ns
—
t_CYC
1. V_SS = 0 Vdc; timing shown with respect to 20% V_DD and 70% V_DD unless otherwise noted.
2. No more than 10% duty cycle deviation from 50%.
3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
4. Minimum pulse width is for guaranteed interrupt. It is possible for a smaller pulse width to be recognized.
20.8 3.3-Volt Control Timing
Characteristic⁽¹⁾
Symbol
Min
Max
Unit
Frequency of operation
Crystal option
External clock option⁽²⁾
f_OSC
32
100
kHz
dc
16.4
MHz
Internal operating frequency
Internal clock period (1/f_OP)
RESET input pulse width low⁽³⁾
f_OP (f_Bus)
—
t_CYC
244
t_IRL
125
4.1
MHz
—
ns
—
ns
IRQ interrupt pulse width low⁽⁴⁾ (edge-triggered)
t_ILIH
125
—
ns
IRQ interrupt pulse period
t_ILIL
Note 5
—
t_CYC
1. V_SS = 0 Vdc; timing shown with respect to 20% V_DD and 70% V_DD unless otherwise noted.
2. No more than 10% duty cycle deviation from 50%.
3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
4. Minimum pulse width is for guaranteed interrupt. It is possible for a smaller pulse width to be recognized.
t_RL
RST
t_ILIL
t_ILIH
IRQ
Figure 20-1. RST and IRQ Timing
MC68HC908GR16 Data Sheet, Rev. 5.0
Freescale Semiconductor
259