MC68HC908GR16 Datasheet, PDF (32/276 Pages) Motorola, Inc – Microcontrollers

Memory
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$001E
Configuration Register 2 Read: 0
(CONFIG2)⁽¹⁾ _Write:
See page 80.
0
0
0
R
TMBCLK- OSCENIN- ESCIBD-
SEL
STOP
SRC
Reset: 0
0
0
0
0
0
0
1
$001F
Configuration Register 1 ^Read:
(CONFIG1)⁽¹⁾ Write:
See page 80. _Reset:
COPRS
0
LVISTOP
0
LVIRSTD
0
LVIPWRD
0
LVI5OR3
(Note 1)
0
SSREC
0
STOP
0
COPD
0
1. One-time writable register after each reset, except LVI5OR3 bit. LVI5OR3 bit is only reset via POR (power-on reset).
$0020
Timer 1 Status and Control ^Read:
Register (T1SC) Write:
See page 231. _Reset:
$0021
Timer 1 Counter ^Read:
Register High (T1CNTH) Write:
See page 232. _Reset:
$0022
Timer 1 Counter ^Read:
Register Low (T1CNTL) Write:
See page 232. _Reset:
$0023
Timer 1 Counter Modulo ^Read:
Register High (T1MODH) Write:
See page 233. _Reset:
$0024
Timer 1 Counter Modulo ^Read:
Register Low (T1MODL) Write:
See page 233. _Reset:
Timer 1 Channel 0 Status and ^Read:
$0025 Control Register (T1SC0) Write:
See page 233. _Reset:
$0026
Timer 1 Channel 0 ^Read:
Register High (T1CH0H) Write:
See page 236. _Reset:
$0027
Timer 1 Channel 0 ^Read:
Register Low (T1CH0L) Write:
See page 236. _Reset:
Timer 1 Channel 1 Status and ^Read:
$0028 Control Register (T1SC1) Write:
See page 234. _Reset:
TOF
0
0
Bit 15
0
Bit 7
0
Bit 15
1
Bit 7
1
CH0F
0
0
Bit 15
Bit 7
CH1F
0
0
0
0
TOIE TSTOP
PS2
TRST
0
1
0
0
0
14
13
12
11
10
0
0
0
0
0
6
5
4
3
2
0
14
1
6
1
CH0IE
0
14
6
CH1IE
0
0
0
0
0
13
12
11
10
1
1
1
1
5
4
3
2
1
1
1
1
MS0B MS0A ELS0B ELS0A
0
0
0
0
13
12
11
10
Indeterminate after reset
5
4
3
2
Indeterminate after reset
0
MS1A ELS1B ELS1A
0
0
0
0
PS1
PS0
0
0
9
Bit 8
0
0
1
Bit 0
0
9
1
1
1
TOV0
0
9
0
Bit 8
1
Bit 0
1
CH0MAX
0
Bit 8
1
Bit 0
TOV1
0
CH1MAX
0
= Unimplemented
R = Reserved U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 8)
MC68HC908GR16 Data Sheet, Rev. 5.0
32
Freescale Semiconductor