MC68HC908GR16 Datasheet, PDF (240/276 Pages) Motorola, Inc – Microcontrollers

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19.2.2.2 Break Address Registers
The break address registers (BRKH and BRKL) contain the high and low bytes of the desired breakpoint
address. Reset clears the break address registers.
Address: $FE09
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 19-4. Break Address Register High (BRKH)
Address: $FE0A
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 19-5. Break Address Register Low (BRKL)
19.2.2.3 Break Auxiliary Register
The break auxiliary register (BRKAR) contains a bit that enables software to disable the COP while the
MCU is in a state of break interrupt with monitor mode.
Address: $FE02
Bit 7
6
5
4
3
2
1
Read: 0
0
0
0
0
0
0
Write:
Reset: 0
0
0
0
0
0
0
= Unimplemented
Figure 19-6. Break Auxiliary Register (BRKAR)
Bit 0
BDCOP
0
BDCOP — Break Disable COP Bit
This read/write bit disables the COP during a break interrupt. Reset clears the BDCOP bit.
1 = COP disabled during break interrupt
0 = COP enabled during break interrupt.
MC68HC908GR16 Data Sheet, Rev. 5.0
240
Freescale Semiconductor