MC68HC05SU3A Datasheet, PDF (8/80 Pages) Freescale Semiconductor, Inc – Fully static chip design featuring the industry standard 8-bit M68HC05 core

Freescale Semiconductor, Inc.
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4.2 RAM ......................................................................................................................4-1
4.3 ROM ......................................................................................................................4-1
4.4 Memory Map .........................................................................................................4-2
4.5 I/O Registers Summary .........................................................................................4-3
5
RESETS AND INTERRUPTS
5.1 RESETS ................................................................................................................5-1
5.1.1 Power-On Reset (POR) ...................................................................................5-1
5.1.2 RESET Pin.......................................................................................................5-1
5.1.3 Low Voltage Reset (LVR) .................................................................................5-2
5.2 INTERRUPTS........................................................................................................5-2
5.2.1 Non-maskable Software Interrupt (SWI) ..........................................................5-3
5.2.2 Maskable Hardware Interrupts.........................................................................5-5
5.2.2.1
External Interrupt (IRQ)..............................................................................5-5
5.2.2.2
External Interrupt 2 (IRQ2).........................................................................5-7
5.2.2.3
Timer Interrupt............................................................................................5-7
5.2.2.4
Keyboard Interrupt (KBI) ............................................................................5-8
6
TIMER
6.1 Timer Overview .....................................................................................................6-1
6.2 Timer Control Register (TCR)................................................................................6-3
6.3 Timer Data Register (TDR)....................................................................................6-4
6.4 Operation during Low Power Modes .....................................................................6-4
7
CPU CORE AND INSTRUCTION SET
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
Registers ...............................................................................................................7-1
Accumulator (A) ...............................................................................................7-1
Index register (X) .............................................................................................7-2
Program counter (PC)......................................................................................7-2
Stack pointer (SP)............................................................................................7-2
Condition code register (CCR).........................................................................7-2
Instruction set ........................................................................................................7-3
Register/memory Instructions ..........................................................................7-4
Branch instructions ..........................................................................................7-4
Bit manipulation instructions ............................................................................7-4
Read/modify/write instructions.........................................................................7-4
Control instructions ..........................................................................................7-4
TPG
MC68HC05SU3A
ii
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