MC68HC05SU3A Datasheet, PDF (29/80 Pages) Freescale Semiconductor, Inc – Fully static chip design featuring the industry standard 8-bit M68HC05 core

Freescale Semiconductor, Inc.
4
MEMORY AND REGISTERS
4
The MC68HC05SU3A has 8K-bytes of addressable memory, consisting of I/O registers, user
ROM, user RAM, and self-check ROM. Figure 4-1 shows the memory map for MC68HC05SU3A
device.
4.1
I/O Registers
The I/O, status and control registers are located within the first 16 bytes of memory, from $0000
to $000F. These are shown in the memory map in Figure 4-1; and a summary of the register
outline is shown in Table 4-1. Reading from unimplemented bits will return unknown states, and
writing to unimplemented bits will be ignored.
4.2
RAM
The user RAM (including the stack) consists of 192 bytes. It is separated into two blocks at
locations $0010 to $008F, and $00C0 to $00FF. The stack begins at address $00FF and proceeds
down to $00C0.
4.3
ROM
The user ROM consists of 3840 bytes of memory, from $1000 to $1EFF. Twelve bytes of user
vectors are also available, from $1FF4 to $1FFF.
Note:
Using the stack area for data storage or temporary work locations requires care to
prevent the data from being overwritten due to stacking from an interrupt or subroutine
call.
TPG
MC68HC05SU3A
MEMORY AND REGISTERS
For More Information On This Product,
4-1
Go to: www.freescale.com