MC68HC05SU3A Datasheet, PDF (40/80 Pages) Freescale Semiconductor, Inc – Fully static chip design featuring the industry standard 8-bit M68HC05 core

Freescale Semiconductor, Inc.
TIF — Timer Interrupt Flag
1 (set) – A timer interrupt (timer overflow) has occurred.
0 (clear) – A timer interrupt (timer overflow) has not occurred.
The I-bit in the CCR must be cleared in order for the timer interrupt to be processed. The interrupt
will vector to the interrupt service routine at the address specified by the contents in $1FF6-$1FF7.
5.2.2.4 Keyboard Interrupt (KBI)
Keyboard interrupt function is associated with Port A pins. The keyboard interrupt function is
5
enabled by setting the keyboard interrupt enable bit KBIE (bit 7 of MCR at $0C) and the individual
enable bits KBE0-KBE7 (bits 0-7 of KBIM at $0B). When the KBEx bit is set, the corresponding
Port A pin will be configured as an input pin, regardless of the DDR setting, and a 20KΩ pull-up
resistor is connected to the pin, as shown in Figure 5-4. When a high to low transition is sensed
on the pin, a keyboard interrupt will be generated. An interrupt to the CPU will be generated if the
I-bit in the CCR is cleared.
The keyboard interrupt flag should be cleared in the interrupt service routine (by writing a “1” to
KBIC bit in the MCR at $0C) after the key is debounced. Debouncing will avoid spurious false
triggering.
The keyboard interrupt is negative-edge sensitive only, and the interrupt service routine is
specified by the contents in $1FF4-$1FF5.
KBEx of KBIM
&
V_DD
&
&
Keyboard
Interrupt
request
&
KBIE bit of MCR
($0C bit 7)
&
DDR0-DDR7
Internal Data bit (0-7), Port A
20KΩ
Pad Logic
1 input for each of PA0-PA7
(8 input NAND)
PAx
Figure 5-4 Keyboard Interrupt Circuitry
TPG
RESETS AND INTERRUPTS
MC68HC05SU3A
5-8
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