MC68HC05SU3A Datasheet, PDF (53/80 Pages) Freescale Semiconductor, Inc – Fully static chip design featuring the industry standard 8-bit M68HC05 core

Freescale Semiconductor, Inc.
Table 7-5 Read/modify/write instructions
Inherent
(A)
Addressing modes
Inherent
(X)
Direct
Indexed
(no
offset)
Indexed
(8-bit
offset)
Function
Increment
INC 4C 1 3 5C 1 3 3C 2 5 7C 1 5 6C 2 6
Decrement
DEC 4A 1 3 5A 1 3 3A 2 5 7A 1 5 6A 2 6
Clear
CLR 4F 1 3 5F 1 3 3F 2 5 7F 1 5 6F 2 6
Complement
COM 43 1 3 53 1 3 33 2 5 73 1 5 63 2 6
Negate (two’s complement) NEG 40 1 3 50 1 3 30 2 5 70 1 5 60 2 6
Rotate left through carry
ROL 49 1 3 59 1 3 39 2 5 79 1 5 69 2 6
Rotate right through carry
ROR 46 1 3 56 1 3 36 2 5 76 1 5 66 2 6
Logical shift left
LSL 48 1 3 58 1 3 38 2 5 78 1 5 68 2 6
Logical shift right
LSR 44 1 3 54 1 3 34 2 5 74 1 5 64 2 6
Arithmetic shift right
Test for negative or zero
ASR 47 1 3 57 1 3 37 2 5 77 1 5 67 2 6
TST 4D 1 3 5D 1 3 3D 2 4 7D 1 4 6D 2 5
7
Multiply
MUL 42 1 11
Table 7-6 Control instructions
Function
Transfer A to X
Transfer X to A
Set carry bit
Clear carry bit
Set interrupt mask bit
Clear interrupt mask bit
Software interrupt
Return from subroutine
Return from interrupt
Reset stack pointer
No-operation
Stop
Wait
Mnemonic
TAX
TXA
SEC
CLC
SEI
CLI
SWI
RTS
RTI
RSP
NOP
STOP
WAIT
Inherent addressing mode
Opcode # Bytes # Cycles
97
1
2
9F
1
2
99
1
2
98
1
2
9B
1
2
9A
1
2
83
1
10
81
1
6
80
1
9
9C
1
2
9D
1
2
8E
1
2
8F
1
2
MC68HC05SU3A
CPU CORE AND INSTRUCTION SET
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TPG
7-7