MC68HC05SU3A Datasheet, PDF(37/80 Page) Freescale Semiconductor, Inc – Fully static chip design featuring the industry standard 8-bit M68HC05 core

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MC68HC05SU3A Datasheet, PDF (37/80 Pages) Freescale Semiconductor, Inc – Fully static chip design featuring the industry standard 8-bit M68HC05 core

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Freescale Semiconductor, Inc.

5.2.2 Maskable Hardware Interrupts

If the interrupt mask bit (I-bit) of the CCR is set, all maskable interrupts are masked. Clearing the

I-bit allows interrupt processing to occur.

Note:

The internal interrupt latch is cleared in the ï¬rst part of the interrupt service routine;

therefore, one external interrupt pulse could be latched and serviced as soon as the

I-bit is cleared.

5.2.2.1 External Interrupt (IRQ)

The external interrupt IRQ is controlled by two bits in the Miscellaneous Control Register ($0C).

Address bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State

on reset

Miscellaneous Control Register $0C KBIE KBIC INTO INTE LVRE SM IRQ2F IRQ2E 0001 0000

INTE â INTerrupt Enable

1 (set) â External interrupt IRQ is enabled.

0 (clear) â External interrupt is disabled.

The external IRQ is default enabled at power-on reset.

INTO â INTerrupt Option

1 (set) â Negative-edge sensitive triggering for IRQ.

0 (clear) â Negative-level sensitive triggering for IRQ.

When the signal of the external interrupt pin, IRQ, satisï¬es the condition selected, an external

interrupt occurs. The actual processor interrupt is generated only if the interrupt mask bit of the

condition code register is also cleared. When the interrupt is recognized, the current state of the

processor is pushed onto the stack and the interrupt mask bit in the Condition Code Register is

set. This masks further interrupts until the present one is serviced. The service routine address is

speciï¬ed by the contents in $1FFA-$1FFB.

The interrupt logic recognizes negative edge transitions and pulses (special case of negative

edges) on the external interrupt line. Figure 5-3 shows both a block diagram and timing for the

interrupt line (IRQ) to the processor. The ï¬rst method is used if pulses on the interrupt line are

spaced far enough apart to be serviced. The minimum time between pulses is equal to the number

of cycles required to execute the interrupt service routine plus 21 cycles. Once a pulse occurs, the

next pulse should not occur until the MCU software has exited the routine (an RTI occurs). The

second conï¬guration shows several interrupt lines wired-OR to perform the interrupt at the

processor. Thus, if the interrupt lines remain low after servicing one interrupt, the next interrupt is

recognized.

MC68HC05SU3A

RESETS AND INTERRUPTS

For More Information On This Product,

Go to: www.freescale.com

TPG

5-5

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