MC68HC05SU3A Datasheet, PDF (46/80 Pages) Freescale Semiconductor, Inc – Fully static chip design featuring the industry standard 8-bit M68HC05 core

Freescale Semiconductor, Inc.
PR2:PR0
These three bits enable the program to select the division ratio of the prescaler. On reset, these
three bits are set to “100”, which corresponds to a division ratio of 16.
6
6.3
PR2
PR1
PR0
Divide Ratio
0
0
0
1
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
16
1
0
1
32
1
1
0
64
1
1
1
128
Timer Data Register (TDR)
The TDR is a read/write register which contains the current value of the 8-bit count-down timer
counter when read. Reading this register does not disturb the counter operation.
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$08 TD7 TD6 TD5 TD4 TD3 TD2 TD1 TD0 1111 1111
6.4
Operation during Low Power Modes
The timer ceases counting in STOP mode. When STOP mode is exited by an external interrupt
(IRQ or KBI), the internal oscillator will resume its operation, followed by internal processor
stabilization delay. The timer is then cleared to zero and resumes its operation. The TIF bit in the
TCR will be set. To avoid generating a timer interrupt when exiting STOP mode, it is recommended
to set the TIM bit prior entering STOP mode. After exiting STOP mode TIF bit can then be cleared.
The CPU clock halts during the WAIT mode, but the timer remains active. If the interrupts are
enabled, the timer interrupt will cause the processor to exit the WAIT mode.
TPG
TIMER
MC68HC05SU3A
6-4
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