MC68HC05SU3A Datasheet, PDF (54/80 Pages) Freescale Semiconductor, Inc – Fully static chip design featuring the industry standard 8-bit M68HC05 core

Freescale Semiconductor, Inc.
Table 7-7 Instruction set
Addressing modes
Condition codes
Mnemonic
INH IMM DIR EXT REL IX IX1 IX2 BSC BTB H I N Z C
ADC
◊ • ◊◊◊
ADD
◊ • ◊◊◊
AND
• • ◊◊ •
ASL
• • ◊◊◊
ASR
• • ◊◊◊
BCC
•••••
BCLR
•••••
BCS
•••••
BEQ
•••••
BHCC
•••••
BHCS
•••••
BHI
•••••
BHS
•••••
BIH
•••••
7
BIL
BIT
•••••
• • ◊◊ •
BLO
•••••
BLS
•••••
BMC
•••••
BMI
•••••
BMS
•••••
BNE
•••••
BPL
•••••
BRA
•••••
BRN
•••••
BRCLR
• • • •◊
BRSET
• • • •◊
BSET
•••••
BSR
•••••
CLC
• • • •0
CLI
•0• • •
CLR
• •01•
CMP
• • ◊◊◊
Address mode abbreviations
BSC Bit set/clear
IMM Immediate
BTB Bit test & branch
IX Indexed (no offset)
DIR Direct
IX1 Indexed, 1 byte offset
EXT Extended
IX2 Indexed, 2 byte offset
INH Inherent
REL Relative
Not implemented
Condition code symbols
H Half carry (from bit 3)
◊
Tested and set if true,
cleared otherwise
I Interrupt mask
• Not affected
N Negate (sign bit)
? Load CCR from stack
Z Zero
0 Cleared
C Carry/borrow
1 Set
TPG
CPU CORE AND INSTRUCTION SET
MC68HC05SU3A
7-8
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