MC68HC05SU3A Datasheet, PDF (63/80 Pages) Freescale Semiconductor, Inc – Fully static chip design featuring the industry standard 8-bit M68HC05 core

Freescale Semiconductor, Inc.
8.3
SLOW Mode
The SLOW mode function is controlled by the SM bit in the Miscellaneous Control Register. When
the SM bit is set, the internal bus clock is divided by 16, resulting to a frequency equal to the
oscillator frequency divide by 32. This feature permits a slow down of all the internal operations
and thus reduces power consumption — particularly useful while in WAIT mode. The SM bit is
automatically cleared while going to STOP mode.
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Miscellaneous Control Register $0C KBIE KBIC INTO INTE LVRE SM IRQ2F IRQ2E 0001 0000
SM — Slow Mode
1 (set) – Slow mode enabled. Internal bus frequency f_OP=f_OSC ÷ 32.
0 (clear) – Slow mode disabled. Internal bus frequency f_OP=f_OSC ÷ 2.
8
TPG
MC68HC05SU3A
LOW POWER MODES
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8-3
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