MC68HC05SU3A Datasheet, PDF (55/80 Pages) Freescale Semiconductor, Inc – Fully static chip design featuring the industry standard 8-bit M68HC05 core

Freescale Semiconductor, Inc.
Table 7-7 Instruction set (Continued)
Addressing modes
Condition codes
Mnemonic
INH IMM DIR EXT REL IX IX1 IX2 BSC BTB H I N Z C
COM
• • ◊◊1
CPX
• • ◊◊◊
DEC
• • ◊◊ •
EOR
• • ◊◊ •
INC
• • ◊◊ •
JMP
•••••
JSR
•••••
LDA
• • ◊◊ •
LDX
• • ◊◊ •
LSL
• • ◊◊◊
LSR
• • 0◊◊
MUL
0• • •0
NEG
• • ◊◊◊
NOP
•••••
ORA
ROL
• • ◊◊ •
• • ◊◊◊
7
ROR
• • ◊◊◊
RSP
•••••
RTI
?????
RTS
•••••
SBC
• • ◊◊◊
SEC
• • • •1
SEI
•1• • •
STA
• • ◊◊ •
STOP
•0• • •
STX
• • ◊◊ •
SUB
• • ◊◊◊
SWI
•1• • •
TAX
•••••
TST
• • ◊◊ •
TXA
•••••
WAIT
•0• • •
Address mode abbreviations
BSC Bit set/clear
IMM Immediate
BTB Bit test & branch
IX Indexed (no offset)
DIR Direct
IX1 Indexed, 1 byte offset
EXT Extended
IX2 Indexed, 2 byte offset
INH Inherent
REL Relative
Not implemented
Condition code symbols
H Half carry (from bit 3)
◊
Tested and set if true,
cleared otherwise
I Interrupt mask
• Not affected
N Negate (sign bit)
? Load CCR from stack
Z Zero
0 Cleared
C Carry/borrow
1 Set
MC68HC05SU3A
CPU CORE AND INSTRUCTION SET
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TPG
7-9