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MC68HC05SU3A Datasheet, PDF (43/80 Pages) Freescale Semiconductor, Inc – Fully static chip design featuring the industry standard 8-bit M68HC05 core | |||
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Freescale Semiconductor, Inc.
6
TIMER
This section describes the operation of the 8-bit count-down timer in the MC68HC05SU3A.
6.1
Timer Overview
6
The MC68HC05SU3A timer block diagram is shown in Figure 6-1. The timer contains a single 8-bit
software programmable count-down counter with a 7-bit software selectable prescaler. The
counter may be preset under software control and decrements towards zero. When the counter
decrements to zero, the timer interrupt ï¬ag (TIF bit in Timer Control Register, TCR) is set. Once
timer interrupt ï¬ag is set, an interrupt is generated to the CPU only if the TIM bit in the TCR and
I-bit in the CCR are cleared. When a interrupt is recognized, after completion of the current
instruction, the processor proceeds to store the appropriate registers on the stack and then
fetches the timer interrupt vector from locations $1FF6 and $1FF7.
The counter continues to count after it reaches zero, allowing the software to determine the
number of internal or external clocks since the timer interrupt ï¬ag was set. The counter may be
read at any time by the processor without disturbing the count. The contents of the counter
become stable prior to the read portion of a cycle and do not change during the read. The timer
interrupt ï¬ag remains set until cleared by the software. If a write occurs before the timer interrupt
is served, the interrupt is lost. The timer interrupt ï¬ag may also be used as a scanned status bit in
a non-interrupt mode of operation.
The prescaler is a 7-bit divider which is used to extend the maximum length of the timer. Bit 0, 1,
2 (PR0, PR1, PR2) of TCR are programmed to choose the appropriate prescaler output which is
used as the 8-bit counter clock input. The processor cannot write into or read from the prescaler;
however, its contents can be cleared to all zeros by writing to the PRER bit in the TCR. This will
allow for truncation-free counting.
The input clock for the timer sub-system is selectable from internal, external, or a combination of
internal and external sources. The TCEX and TINE bits in the Timer Control Register selects the
timer input clock.
TPG
MC68HC05SU3A
TIMER
For More Information On This Product,
6-1
Go to: www.freescale.com
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