MC68HC05SU3A Datasheet, PDF (26/80 Pages) Freescale Semiconductor, Inc – Fully static chip design featuring the industry standard 8-bit M68HC05 core

Freescale Semiconductor, Inc.
3
INTERNAL
MC68HC05
CONNECTIONS
DATA DIRECTION
REGISTER BIT
LATCHED OUTPUT
DATA BIT
OUTPUT
INPUT
REGISTER
BIT
INPUT I/O
I/O PIN
Figure 3-1 Port I/O Circuitry
3.1.2 Port Data Direction Registers
Each port pin may be programmed as an input by clearing the corresponding bit in the DDR, or
programmed as an output by setting the corresponding bit in the DDR. The DDR for Port A, B, C,
and D are located at $04, $05, $06 and, $07 respectively. The DDRs are cleared by reset.
Note:
A “glitch” may occur on an I/O pin when selecting from an input to an output unless the
data register is first preconditioned to the desired state before changing the
corresponding DDR bit from a “0” to a “1”.
3.2
Port A — Keyboard Interrupts (KBI)
Port A is configured for use as keyboard interrupts when the KBIE bit is set in the Miscellaneous
Control Register (MCR). Individual keyboard interrupt port pins are also maskable by setting
corresponding bits in the Keyboard Interrupt Mask Register.
See Section 5.2.2.4 for details on the keyboard interrupts.
3.3
PD6 — IRQ2
The port pin PD6 is configured as IRQ2 by setting the IRQ2E bit in the MCR. The external interrupt
IRQ2 behaves similar to IRQ except it is edge-triggered only, and does not have wake-up function
in STOP mode.
See Section 5.2.2.2 for details on the external interrupt IRQ2.
TPG
INPUT/OUTPUT PORTS
MC68HC05SU3A
3-2
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