MC68HC05SU3A Datasheet, PDF (49/80 Pages) Freescale Semiconductor, Inc – Fully static chip design featuring the industry standard 8-bit M68HC05 core

Freescale Semiconductor, Inc.
Interrupt (I)
When this bit is set, all maskable interrupts are masked. If an interrupt occurs while this bit is set,
the interrupt is latched and remains pending until the interrupt bit is cleared.
Negative (N)
When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was
negative.
Zero (Z)
When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was
zero.
Carry/borrow (C)
When set, this bit indicates that a carry or borrow out of the arithmetic logical unit (ALU) occurred
during the last arithmetic operation. This bit is also affected during bit test and branch instructions
and during shifts and rotates.
7
7.2
Instruction set
The MCU has a set of 62 basic instructions. They can be grouped into five different types as
follows:
– Register/memory
– Read/modify/write
– Branch
– Bit manipulation
– Control
The following paragraphs briefly explain each type. All the instructions within a given type are
presented in individual tables.
This MCU uses all the instructions available in the M146805 CMOS family plus one more: the
unsigned multiply (MUL) instruction. This instruction allows unsigned multiplication of the contents
of the accumulator (A) and the index register (X). The high-order product is then stored in the
index register and the low-order product is stored in the accumulator. A detailed definition of the
MUL instruction is shown in Table 7-1.
MC68HC05SU3A
CPU CORE AND INSTRUCTION SET
For More Information On This Product,
Go to: www.freescale.com
TPG
7-3