MC68HC05SU3A Datasheet, PDF(34/80 Page) Freescale Semiconductor, Inc – Fully static chip design featuring the industry standard 8-bit M68HC05 core

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MC68HC05SU3A Datasheet, PDF (34/80 Pages) Freescale Semiconductor, Inc – Fully static chip design featuring the industry standard 8-bit M68HC05 core

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Freescale Semiconductor, Inc.

5.1.3 Low Voltage Reset (LVR)

When the LVR function is enabled, an internal reset is generated if the supply voltage, VDD, drops

below VLVR. (See Section 11 for value of VLVR).

This LVR function is enabled by setting the LVRE bit in the Miscellaneous Control Register.

Address bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State

on reset

Miscellaneous Control Register $0C KBIE KBIC INTO INTE LVRE SM IRQ2F IRQ2E 0001 0000

LVRE â Low Voltage Reset Enable

1 (set) â Low Voltage Reset function enabled.

0 (clear) â Low Voltage Reset function disabled.

5.2

INTERRUPTS

The MC68HC05SU3A MCU can be interrupted by different sources â four maskable hardware

interrupt and one non-maskable software interrupt:

â¢ Software Interrupt Instruction (SWI)

â¢ External signal on IRQ pin

â¢ External signal on IRQ2 pin

â¢ TImer Overï¬ow

â¢ Keyboard

If the interrupt mask bit (I-bit) in the Condition Code Register (CCR) is set, all maskable interrupts

are disabled. Clearing the I-bit enables interrupts.

Interrupts cause the processor to save the register contents on the stack and to set the interrupt

mask (I-bit) to prevent additional interrupts. The RTI instruction causes the register contents to be

recovered from the stack and normal processing to resume.

Unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but

are considered pending until the current instruction is complete. The current instruction is the one

already fetched and being operated on. When the current instruction is complete, the processor

checks all pending hardware interrupts. If interrupts are not masked (CCR I-bit clear) the

processor proceeds with interrupt processing; otherwise, the next instruction is fetched and

executed. Table 5-1 shows the relative priority of all the possible interrupt sources. Figure 5-2

shows the interrupt processing ï¬ow.

TPG

RESETS AND INTERRUPTS

MC68HC05SU3A

5-2

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