MC68HC05SU3A Datasheet, PDF (45/80 Pages) Freescale Semiconductor, Inc – Fully static chip design featuring the industry standard 8-bit M68HC05 core

Freescale Semiconductor, Inc.
6.2
Timer Control Register (TCR)
The TCR enables the software to control the operation of the timer.
Address bit 7
$09 TIF
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
TIM TCEX TINE PRER PRE2 PRE1 PRE0 0100 -100
TIF — Timer Interrupt Flag
1 (set) – The timer has reached a count of zero.
0 (clear) – The timer has not reached a count of zero.
The timer interrupt flag is set when the 8-bit counter decrements to zero. This bit is cleared on
reset, or by writing a “0” to the TIF bit.
TIM — Timer Interrupt Mask
6
1 (set) – Timer interrupt request to the CPU is masked (disabled).
0 (clear) – Timer interrupt request to the CPU is not masked (enabled).
A reset sets this bit to one; it must then be cleared by software to enable the timer interrupt to the
CPU. This timer interrupt mask only masks timer interrupt request to the CPU, and does not affect
counting of the 8-bit counter or the setting of TIF.
TCEX — Timer Clock EXternal
TINE — Timer INput Enable
These two bits selects the source of the timer clock. Reset or power-on clears these bits to zero.
TCEX TINE
Clock Source
0
0 Internal clock to timer
0
1 “AND” of internal clock and TIMER pin to timer
1
0 Input clock to timer disabled
1
1 TIMER pin to timer
PRER — PREscaler Reset
Writing a “1” to this write-only bit will reset the prescaler to zero, which is necessary for any new
counts set by writing to the Timer Data Register.This bit always reads as zero, and is not affected
by reset.
TPG
MC68HC05SU3A
TIMER
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6-3
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