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MC68HC05SU3A Datasheet, PDF (70/80 Pages) Freescale Semiconductor, Inc – Fully static chip design featuring the industry standard 8-bit M68HC05 core
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Freescale Semiconductor, Inc.
10
10.3
DC Electrical Characteristics
Table 10-1 DC Electrical Characteristics
(VDD=5.0Vdc ±10%, VSS=0Vdc, temperature range=0 to 70°C)
CHARACTERISTICS
SYMBOL MINIMUM TYPICAL MAXIMUM UNIT
Output voltage
ILOAD = –10µA
ILOAD = +10µA
Output high voltage (ILOAD=–0.8mA): All Ports
Output low voltage (ILOAD=+1.6mA): All Ports
Output high current
(VOH=2.5V) All ports
(VOH=2.0V) PB5-PB7 in low-current mode (25°C)
(VOH=2.0V) PB5-PB7 in low-current mode (0 to 70°C)
Output low current
(VOL=2.5V) All ports, except PB0 and PB1
(VOL=3.0V) PB5-PB7 in low-current mode
(VOL=2.5V) PB0, PB1
(VOL=0.4V) PB0, PB1
Total I/O port current
Either source or sink
VOH
VOL
VOH
VOL
IOH
IOL
IPORT
VDD – 0.1
—
—
—
VDD – 0.8
—
—
—
7
10
1.5
1.75
1.25
1.75
7
10
2
3.5
40
70
10
20
—
100
—
V
0.1
V
—
V
0.4
V
30
mA
5
mA
5
mA
30
mA
4.8
mA
—
mA
—
mA
—
mA
Input high voltage
PA0-PA7, PB0, PB1, IRQ, RESET, OSC1
VIH
0.7 × VDD
—
VDD
V
Input low voltage
PA0-PA7, PB0, PB1, IRQ, RESET, OSC1
VIL
VSS
—
0.2 × VDD
V
Supply current:
Run
Wait
Stop 25°C
0°C to +70°C (Standard)
—
5.0
7.5
mA
IDD
—
1.3
2.0
mA
—
8
20
µA
—
10
30
µA
I/O ports high-Z leakage current
PA0-PA7, PB2-PB7, PC0-PC7, PD0-PD7
IIL
—
—
± 10
µA
Input current
IRQ, OSC1
IIN
—
—
±2
µA
Capacitance
Ports (as input or output)
RESET, IRQ, OSC1, OSC2
Low voltage reset threshold
Pull-up resistor
PA0-PA7, PB2-PB7, PC0-PC7, PD0-PD7
PB0, PB1
RESET
IRQ
COUT
—
—
12
pF
CIN
—
—
8
pF
VLVR
2.8
3.5
4.2
V
15
20
90
KΩ
RPU
1.6
1.9
2.9
KΩ
20
60
150
KΩ
60
100
300
KΩ
Notes:
(1) All values shown reflect average measurements.
(2) Typical values at midpoint of voltage range, 25°C only.
(3) Wait IDD: Only timer system active.
(4) Wait, Stop IDD: All ports configured as inputs, VIL=0.2Vdc, VIH=VDD–0.2Vdc.
(5) Run (operating) IDD, Wait IDD: Measured using external square wave clock source to OSC1 (fOSC=2.0MHz), all inputs 0.2Vdc from rail; no DC loads, less than 50pF on
all outputs, CL=20pF on OSC2.
(6) Stop IDD measured with OSC1=VSS.
(7) Wait IDD is affected linearly by the OSC2 capacitance.
TPG
ELECTRICAL SPECIFICATIONS
MC68HC05SU3A
10-2
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