MC68HC05SU3A Datasheet, PDF (38/80 Pages) Freescale Semiconductor, Inc – Fully static chip design featuring the industry standard 8-bit M68HC05 core

Freescale Semiconductor, Inc.
INTO BIT
V_DD
V_DD
100K
D
Q
IRQ
C
Q
R
&
+
&
I-BIT (CCR)
&
EXTERNAL
INTERRUPT
REQUEST
5
POWER-ON RESET
+
EXTERNAL RESET
EXTERNAL INTERRUPT
BEING SERVICED (IRQ ONLY)
(a) Interrupt Function Diagram
IRQ
Wired ORed
Interrupt signals
IRQ
t_ILIH
t_ILIL
t_ILIH
EDGE SENSITIVE TRIGGER
CONDITION
The minimum pulse width t_ILIH is either
125ns (V_DD=5V) or 250ns (V_DD=3V).
The period t_ILIL should not be less than
the number of tcyc cycles it takes to ex-
ecute the interrupt service routine plus
21 t_CYC cycles.
LEVEL SENSITIVE TRIGGER
CONDITION
if after servicing an interrupt the
external interrupt pin (IRQ) remains
low, then the next interrupt is
recognized. Normally used with pull-up
resistors for wired-OR connection.
(b) Interrupt Mode Diagram
Figure 5-3 External Interrupt
TPG
RESETS AND INTERRUPTS
MC68HC05SU3A
5-6
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