MC68HC05SU3A Datasheet, PDF (61/80 Pages) Freescale Semiconductor, Inc – Fully static chip design featuring the industry standard 8-bit M68HC05 core

Freescale Semiconductor, Inc.
8
LOW POWER MODES
The MC68HC05SU3A has three low-power operating modes. The WAIT and STOP instructions
provide two modes that reduce the power required for the MCU by stopping various internal clocks
and/or the on-chip oscillator. The flow of the STOP and WAIT modes is shown in Figure 8-1. The
third low-power operating mode is the SLOW mode.
8.1
STOP Mode
Execution of the STOP instruction places the MCU in its lowest power consumption mode. In the
STOP mode the internal oscillator is turned off, halting all internal processing.
When the CPU enters STOP mode the I-bit in the Condition Code Register is cleared
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automatically, so that hardware interrupts, IRQ and KBI can “wake” the MCU. All other registers
and memory contents remain unaltered. All input/output lines remain unchanged.
The MCU can be brought out of the STOP mode only by a hardware interrupt or an externally
generated reset. When exiting the STOP mode the internal oscillator will resume after a
pre-defined number of internal processor clock cycles, due to oscillator stabilization.
8.2
WAIT Mode
The WAIT instruction places the MCU in a low-power mode, but consumes more power than the
STOP mode. In the WAIT mode the internal processor clock is halted, suspending all processor
and internal bus activities. Other Internal clocks remain active, permitting interrupts to be
generated from the Timer. The Timer may be used to generate a periodic exit from the WAIT mode
or, in conjunction with the external Timer pin, on the occurrence of external events. Execution of
the WAIT instruction automatically clears the I-bit in the Condition Code Register, so that any
hardware interrupt can “wake” the MCU. All other registers, memory, and input/output lines remain
in their previous states.
TPG
MC68HC05SU3A
LOW POWER MODES
For More Information On This Product,
8-1
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