PXD10 Datasheet, PDF (121/130 Pages) Lumins Inc. – 4” Dia.X 6” extruded aluminum step poles

Electrical characteristics
SCK
DO
1
t_CQ
2
3
4
5
6
7
8
t_S
t_H
DI
1. Last address out
2. Address captured at flash
3. Data out from flash
4. Ideal data capture edge
5. Delayed data capture edge with QSPI_SMPR=0x0000_000x
6. Delayed data capture edge with QSPI_SMPR=0x0000_002x
7. Delayed data capture edge with QSPI_SMPR=0x0000_004x
8. Delayed data capture edge with QSPI_SMPR=0x0000_006x
Figure 44. QuadSPI input timing diagram
The clock profile in Figure 45 is measured at 30% to 70% levels of VDDE.
t_R
t_F
70%
VDDE
30%
SCK
Figure 45. QuadSPI clock profile
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
121