PXD10 Datasheet, PDF (109/130 Pages) Lumins Inc. – 4” Dia.X 6” extruded aluminum step poles

Electrical characteristics
DCU_VSYNC
DCU_HSYNC
LINE 1 LINE 2 LINE 3 LINE 4
LINE n-1 LINE n
DCU_HSYNC
DCU_DE
DCU_CLK
DCU_LD[23:0]
1
2
3
m-1 m
Figure 29. TFT LCD interface timing overview¹
3.20.3.1 Interface to TFT LCD panels—pixel level timings
Figure 30 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and
data. All parameters shown in the diagram are programmable. This timing diagram corresponds to positive
polarity of the DCU_CLK signal (meaning the data and sync signals change on the rising edge) and
active-high polarity of the DCU_HSYNC, DCU_VSYNC and DCU_DE signals. The user can select the
polarity of the DCU_HSYNC and DCU_VSYNC signals via the SYN_POL register, whether active-high
or active-low. The default is active-high. The DCU_DE signal is always active-high.
Pixel clock inversion and a flexible programmable pixel clock delay are also supported. They are
programmed via the DCU Clock Confide Register (DCCR) in the system clock module.
The DELTA_X and DELTA_Y parameters are programmed via the DISP_SIZE register. The PW_H,
BP_H and FP_H parameters are programmed via the HSYN PARA register. The PW_V, BP_V and FP_V
parameters are programmed via the VSYN_PARA register.
Table 55. LCD interface timing parameters—horizontal and vertical
Symbol C
Parameter
Value
Unit
t_PCP CC D Display pixel clock period
t_PWH CC D HSYNC pulse width
t_BPH CC D HSYNC back porch width
t_FPH CC D HSYNC front porch width
t_SW CC D Screen width
t_HSP CC D HSYNC (line) period
t_PWV CC D VSYNC pulse width
—
ns
PW_H  t_PCP
ns
BP_H  t_PCP
ns
FP_H  t_PCP
ns
DELTA_X  t_PCP
ns
(PW_H + BP_H + FP_H + DELTA_X )  t_PCP
ns
PWVt_HSP
ns
1. In Figure 29, the “DCU_LD[23:0]” signal is an aggregation of the DCU’s RGB signals—DCU_R[0:7], DCU_G[0:7] and
DCU_B[0:7].
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
109