PXD10 Datasheet, PDF (119/130 Pages) Lumins Inc. – 4” Dia.X 6” extruded aluminum step poles

Electrical characteristics
Table 62. I²C Output Timing Specifications — SCL and SDA
No. Symbol C
Parameter
Value
Unit
Min Max
1¹ — CC D Start condition hold time
2¹ — CC D Clock low time
3³ — CC D SCL/SDA rise time
4¹ — CC D Data hold time
5¹ — CC D SCL/SDA fall time
6¹ — CC D Clock high time
7¹ — CC D Data setup time
8¹ — CC D Start condition setup time (for repeated start condition only)
9¹ — CC D Stop condition setup time
6 — IP-Bus Cycle²
10 — IP-Bus Cycle¹
— 99.6
ns
7 — IP-Bus Cycle¹
— 99.5
ns
10 — IP-Bus Cycle¹
2 — IP-Bus Cycle¹
20 — IP-Bus Cycle¹
10 — IP-Bus Cycle¹
NOTES:
1 _{Programming IBFD (I}2_{C bus Frequency Divider) with the maximum frequency results in the minimum output timings}
listed. The I²C interface is designed to scale the data transition time, moving it to the middle of the SCL low period.
The actual position is affected by the prescale and division values programmed in IFDR.
2 _{Inter Peripheral Clock is the clock at which the I}2_{C peripheral is working in the device}
3 _{Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time SCL}
or SDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.
2
6
5
SCL
1
SDA
3
4
7
8
9
Figure 42. I²C input/output timing
3.20.9 QuadSPI timing
The following notes apply to Table 63:
• All data are based on a negative edge data launch from PXD10 and a positive edge data capture as
shown in the timing diagrams.
• Typical values are provided from center-split material at 25 C and 3.3 V. Minimum and maximum
values are from a temperature variation of –45 C to 105 C and the following supply conditions:
— IO voltage: 3.2 V, core supply: 1.2 V
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
119