PXD10 Datasheet, PDF (111/130 Pages) Lumins Inc. – 4” Dia.X 6” extruded aluminum step poles

Electrical characteristics
Table 56. TFT LCD interface timing parameters^1,2,3,4
Symbol C
Parameter
Value
Unit
Min
Typ
Max
t_CKP CC D PDI clock period
_CK CC D PDI clock duty cycle
t_DSU CC D PDI data setup time
t_DHD CC D PDI data access hold time
t_CSU CC D PDI control signal setup time
t_CHD CC D PDI control signal hold time
CC D TFT interface data valid after pixel clock
15.25
—
40
—
9.5
—
4.5
—
9.5
—
4.5
—
—
—
—
ns
60
%
—
ns
—
ns
—
ns
—
ns
6
ns
CC D TFT interface VSYNC valid after pixel clock
—
—
5.5
ns
CC D TFT interface DE valid after pixel clock
—
—
5.6
ns
CC D TFT interface hold time for data and control bits
2
—
—
ns
CC D Relative skew between the data bits
—
—
3.7
ns
NOTES:
1 _{The characteristics in this table are based on the assumption that data is output at positive edge and displays latch}
data on negative edge
2 _{Intra bit skew is less than 2 ns}
3 _{Load CL = 50 pF for panel frequency up to 20 MHz}
4 _{Load CL = 25 pF for panel frequency from 20 to 32 MHz}
DCU_HSYNC
DCU_VSYNC
DCU_DE
DCU_CLK
DCU_LD[23:0]
t_CKH t_CKL
t_CHD t_CSU
t_DSU t_DHD
Figure 32. TFT LCD interface timing parameters
3.20.4 External Interrupt (IRQ) and Non-Maskable Interrupt (NMI) timing
PXD10 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
111