F85226 Datasheet, PDF (9/44 Pages) Feature Integration Technology Inc. – LPC to ISA Bridge

Fintek
IN_t
- TTL level input pin.
IN_ts
- TTL level input pin and schmitt trigger.
P
- Power.
6.1 Power Pin
Feature Integration Technology Inc.
F85226
Pin No.
5, 20, 25, 45, 55, 70, 85, 105, 120
15, 30, 50, 60, 80, 95, 110, 125
Pin Name
VDD3V
GND
Type
P
P
Description
Standard Power Supply Voltage Input with 3.3V.
Ground.
6.2 Power on strapping signal
Pin No
Pin Name
36 80PCS#/KBEN#
Type
I/OD_{24ts_u100k}
(5V-tolerance)
37 ROMCS#/ROM_EN
I/O_24ts
(5V-tolerance)
126
DACK7#/RTCEN#
I/O_{24ts_u100k}
(5V-tolerance)
128
DACK6#/HEFRAS
I/O_{24ts_u100k}
(5V-tolerance)
2
DACK5#/EN_GP2X
I/O_{24ts_u100k}
(5V-tolerance)
PWR
VDD3v
VDD3v
VDD3v
VDD3v
VDD3v
Description
Power-on strapping with external pulled-down resistor 10k will
enable K/B and mouse functions. When it is set, pin 38, 39 and 40
will execute IRQ1, KBCS# and MCCS# signals.
Power-on strapping without internal resister, need external
pulled-up resistor to enable CR03h (BIOS_ROM_EN bit) If there is
a boot-ROM (BIOS). Else if without boot-ROM, please use external
pulled-down 10K resister to disable this BIOS_ROM_EN.
Power-on strapping with external pulled-down 10k resistor will
enable RTC functions. When it is set, pin 64 and 65 will do IRQ8
and RTCCS# signals.
Set this function will change the port that is used to access
configuration registers. Default setting is 4Eh, but by power-on
strapping with a external pulled-down 10k resister change to 2Eh.
Power-on strapping with external pulled-down 10k resistor. Then it
will disable LA [19:17] function and pin108~pin111, pin29 use as
GPIO2X function.
6.3 LPC interface
Pin No.
Pin Name
16-19
LAD[3:0]
13
LFRAME#
21
PCICLK
Type
I/O_24ts
IN_ts
IN_t
PWR
Description
Multiplexed command, address bi-directional data and cycle status.
VDD3v
Through the LPC bus between a host and a peripheral.
Low pulse indicates start of a new cycle or termination of broken
VDD3v
cycle.
PCI clock used for the LPC bus. Same 33MHz clock as PCI clock
VDD3v
on the host. Same clock phase with typical PCI skew.
F85226
4
July, 2007
V0.25P