F85226 Datasheet, PDF (10/44 Pages) Feature Integration Technology Inc. – LPC to ISA Bridge

Fintek
14
PCIRST#
23
SERIRQ
22
LDRQ#
24
PWRDN#
IN_ts
I/O_24ts
O₂₄
IN_ts
Feature Integration Technology Inc.
F85226
PCI system reset used for the LPC bus. The Reset signal line can
VDD3v
be connected to PCIRST# signal on the host.
VDD3v Serial IRQ Input/Output.
VDD3v Encoded DMA Request signal.
VDD3v
Power Down. The signal is active low according to CR 44 Bit 7and
wake-up enable by hardware setting. There are eight different
power-down states (Power down Mode 3).
6.4 ISA interface
Pin No. Pin Name
SA[19:17]
58-56
54-51
49-46
SA[16:0]
44-41
35-31
122-121
119-114
SD[15:0]
75-71
69-67
59 AEN
86 IOR#
84 IOW#
61 IOCHRDY
92 SYSCLK
77 RSTDRV
Type
I/O_{24ts_u100k}
(5V-tolerance)
PWR
Description
VDD3v
System Address Bus. These are the upper addresses that define
the ISA’s byte address space (up to 1 M byte). The SA [19:17] are
at tri-states during PCIRST#.
I/O_{24ts_u100k}
(5V-tolerance)
System Address Bus. These define the ISA’s byte address space
VDD3v
(up to 128K byte). The SD [16:0] are at tri-states during PCIRST#.
I/O_{24ts_u100k}
(5V-tolerance)
System Data Bus. These provide 16-bit data for devices to reside
VDD3v
on the ISA Bus. The SD [15:0] are at tri-states during PCIRST#.
O₂₄
(5V-tolerance)
I/O_{24ts_u100k}
(5V-tolerance)
I/O_{24ts_u100k}
(5V-tolerance)
I/O_24ts
(5V-tolerance)
O₂₄
O₂₄
Address Enable. AEN is asserted during DMA cycles, driven high
VDD3v
during F85226 initiated refresh cycles, driven low upon PCIRST#.
I/O Read. IOR# is asserted to request an ISA I/O slave to drive
VDD3v
data onto the data bus.
I/O Write. IOW# is asserted to request an ISA I/O slave to accept
VDD3v
data from the data bus.
VDD3v
VDD3v
I/O Channel Ready. IOCHDRY asserted indicates that an ISA
slave requires additional wait states. When the F85226 is an ISA
slave, IOCHRDY is an output indicating additional wait states are
required.
ISA System Clock. SYSCLK offers the reference clock to the ISA
bus. The frequency is generated from dividing PCICLK by 3 or 4
(select by CR06 bit7).
Reset Drive. RSTDRV asserted indicates to reset devices that
VDD3v
reside on the ISA Bus while the PCIRST# has been asserted.
F85226
5
July, 2007
V0.25P