F85226 Datasheet, PDF (16/44 Pages) Feature Integration Technology Inc. – LPC to ISA Bridge

Fintek
Feature Integration Technology Inc.
F85226
Size:
LPC host on DMA or bus master on memory transaction issue data size that will be transferred by LAD[1:0]
and LAD[3:2] must be driven 0x00b.
Turn-Around:
LPC host or peripheral will issue two clock wide cycles after turning control over to peripheral or turning
back from peripheral to host. LAD[3:0] should be driven to high level on first cycle and release to tri-state
on next one.
Address:
While doing IO transaction, this duration is four clock wide that indicates 16-bit address, on Memory cycles
there are eight clocks that indicates 32-bit address will be asserted by LPC host or Master. The duration is
not asserted on DMA transaction.
Channel and Terminal count:
Only on DMA transferring, LAD[2:0] signals indicate granted channel in one clock cycle. LAD[3] indicates
Terminal count down.
Data:
Each frame can carry one byte (8 bit), first nibble is Data[7;4] and next is Data[3:0].
SYNC:
LPC host or peripheral can add wait state, response error and ready to accept a frame by LAD[3:0].
0x0h: Ready
0x5h: Short Wait, maximum number of SYNC is 8 clocks.
0x6h: Long Wait, no maximum number.
0x9h: Ready More on DMA transaction.
0xAh: Error, it relates to IOCHK# on ISA interface.
Others: Reserved.
STA : .. Start Cycle
CT : .. Cycle Type and Direction
H_TAR: . Host Turn-Around
P_TAR: Peripheral Turn-Around
LCLK
LFRAME#
LAD[3:0]
STA CT
Addr[15:0]/ [31:0]
Figure: Read Cycles
H_TAR
SYNC
Data[7:0] ^P_TAR
F85226
11
July, 2007
V0.25P