F85226 Datasheet, PDF (17/44 Pages) Feature Integration Technology Inc. – LPC to ISA Bridge

Fintek
Feature Integration Technology Inc.
F85226
LCL
K
LFRAME#
LAD[3:0]
STA CT
Addr[15:0]/ [31:0]
Figure: Write Cycles
Data[7:0] ^H_TAR
SYNC
P_TAR
7.1.1 IO/Memory Read and Write Cycles
When LPC interface Bridge issues IO cycles that meet subtractive decode, F85226 will assert
corresponded IOR#, IOW# , MEMR# ,SMEMR# , MEMW# and SMEMW# then respond by inserting wait
cycles (long wait SYNC). After finishing ISA transaction and there isn’t any valid ISA Wait state inserted, it
responds Ready-state and terminates the cycles. If the host issues 16 bit transfer, F85226 will active
enhance 16-bit transferring function automatically.
7.1.2 DMA Read and Write Cycles
The read transactions transfer data from main memory to peripheral and write cycles transfer data
from peripheral to main memory. DMA requests form ISA interface are delivered by LDRQ# to DMA
controller (like 8237) and the acknowledge responds from LAD [3:0] encoding message. Terminal count is
depended on the counter programmed in DMA controller, when reach the counter threshold, TC is related
to LAD3 and asserted when DMA controller plan to terminal DMA transaction.
7.1.3 Booting Memory Read and Write Cycles
The ISA interface of F85226 can communicate to ISA ROM (System BIOS) with ROMCS#, MEMER#
and MEMW#, BIOS booting cycles of PC system may assert through different cycle type ( like Memory
Read and Firmware Memory Read) , F85226 can perform a positive decoder on specified memory range
included legacy BIOS , extended legacy BIOS and user defined High Memory address.
F85226
12
July, 2007
V0.25P