F85226 Datasheet, PDF (33/44 Pages) Feature Integration Technology Inc. – LPC to ISA Bridge

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Feature Integration Technology Inc.
F85226
8.36 ADDR3 Decoder Mask High Byte Register – Index 0x30
Power-on default [7:0] =0000_0000b
Bit
Name
R/W PWR
Description
7-0 ADDR3_DEC_MASK R/W
VDD3V
This register is used to mask io address bits A7~A0 or memory addrss bits
A23~A16 for specify address decoder, if the corresponding bit of this register is set
to a 1, the corresponding address bits will ignored by the specify address decoder.
For example: If the decoding range is 0x3F8 ~ 0x3FF, you can set 0x03F8 to CR31,
32 and 07h to CR30.
8.37 ADDR3 Decoder Address Low Byte Register – Index 0x31
Power-on default [7:0] =0000_0000b
Bit
Name
R/W PWR
Description
7-0 ADDR3_DEC
This register contains the address for specify decoder.
CR31 Bit [7..0] are used to define low byte of specify address.
CR32 Bit [7..0] are used to define high byte of specify address.
R/W VDD3V ^{For example: Decoding address was set to be 0x3F5h when wrote F5h to CR31}
and 03h to CR32. (The address decoder will decode the match “IO” address that
define in CR31 and CR32 register, but when set CR1B bit6 to 1, The address
decoder will decode the match “memory” address[31:16] that define in CR31 and
CR32 registers).
8.38 ADDR3 Decoder Address High Byte Register – Index 0x32
Power-on default [7:0] =0000_0000b
Bit
Name
R/W PWR
Description
This register contains the address for specify decoder.
CR31 Bit [7..0] are used to define low byte of specify address.
CR32 Bit [7..0] are used to define high byte of specify address.
7-0 ADDR3_DEC
For example: Decoding address was set to be 0x3F5h when wrote F5h to CR31
R/W VDD3V
and 03h to CR32. (The address decoder will decode the match “IO” address that
define in CR31 and CR32 register, but when set CR1B bit6 to 1, The address
decoder will decode the match “memory” address[31:16] that define in CR31 and
CR32 registers).
8.39 ADDR4 Decoder Mask High Byte Register – Index 0x33
Power-on default [7:0] =0000_0000b
Bit
Name
R/W PWR
Description
7-0 ADDR4_DEC_MASK R/W VDD3V This register is used to mask io address bits A7~A0 or memory addrss bits
F85226
28
July, 2007
V0.25P