F85226 Datasheet, PDF (23/44 Pages) Feature Integration Technology Inc. – LPC to ISA Bridge

Fintek
Feature Integration Technology Inc.
= 11 --- 3 SYSCLK s
= 00 --- 4 SYSCLK s
F85226
8.6 System Power down Register – Index 10h
Power-on default [7:0] =0011_0000b
Bit
Name
R/W PWR
7 Reserved
R/W VDD3V
6 SOFT_DOWN
R/W VDD3V
5 EN_CLKOUT_PD
R/W VDD3V
4 EN_SYSCLK_PD
R/W VDD3V
3 EN_REFRESH
R/W VDD3V
2 DIS_CLKOUT2
R/W VDD3V
1 DIS_CLKOUT1
R/W VDD3V
0 EN_GPIO
R/W VDD3V
Description
Set this bit to isolate ISA bus.
Enable CLKOUT1 and CLKOUT2 power down when isolate the ISA bus.
Enable SYSCLK to power down when isolate the ISA bus.
Enable refresh output.
If this bit set to 1, CLKOUT2 will power down.
If this bit set to 1, CLKOUT1 will power down.
Set this bit to enable write command to REG 0x11~0x1A.
8.7 GPIO Port Define Register (Low byte)– Index 11h
Power-on default [7:0] =0000_0000b
Bit
Name
R/W PWR
Description
7-0 GP_ADDR[7:0]
R/W
VDD3V _{User defines port address to control GPIO functions. To control GPIO state}
without entry configure mode. (If GPIO no enable “CR10 bit0”, This register will
read only).
For example: if define GP_ADDR 0x150 in CR11 and CR12t.
If(GPIO output ctrl (REG 0x15, 0x18) set to output mode then:
-o 150 aa (10101010b) to set GP17, GP15, GP13 and GP11 to High.
-o 150 55 (01010101 b) to set GP16, GP14, GP12 and GP10 to High.
-o 151 aa (10101010b) to set GP23 and GP21 to High.
-o 151 55 (01010101 b) to set GP22 and GP20 to High.
If(GPIO output ctrl (REG 0x15, 0x18) set to input mode then:
- i 150 ------show pin states of GP1[7..0].
- i 151------show pin states of GP2[3..0].
F85226
18
July, 2007
V0.25P