F85226 Datasheet, PDF (14/44 Pages) Feature Integration Technology Inc. – LPC to ISA Bridge

Fintek
ROM_EN
Feature Integration Technology Inc.
F85226
Power-on strapping with internal pulled-up resistor will enable
CR03h (BIOS_ROM_EN, BIOS_WR_EN bit). If there is a
boot-ROM (BIOS), else if without boot-ROM, please use external
pulled-down 10K resister to disable this ROM_EN and WR_EN.
GPIO0
38
IRQ1
GPIO1
39
KBCS#
GPIO2
40
MCCS#
GPIO3
62
IRQIN
GPIO4
63
PLED
GPIO5
64
IRQ8
GPIO6
65
RTCCS#
GPIO7
66
IOHCS#
26 14.318M
27 14MOUT 1
I/O_24ts
(5V-tolerance)
I/O_24t
(5V-tolerance)
I/O_24ts
(5V-tolerance)
I/O_24ts
(5V-tolerance)
I/O_24ts
(5V-tolerance)
I/O_24ts
(5V-tolerance)
I/O_24ts
(5V-tolerance)
I/O_24ts
(5V-tolerance)
IN_ts
(5V-tolerance)
O₂₀
VDD3v
General purpose I/O pin 0.
Parallel Interrupt Requested Input 1. This pin is used for specific
K/B functions.
VDD3v
General purpose I/O pin 1.
Decode address 60h and 64h to generate chip selected signal.
Enable by KBEN# power-on setting.
VDD3v
General purpose I/O pin 2.
Decode address 62h and 66h to generate chip selected signal.
Enable by KBEN# power-on setting.
VDD3v
VDD3v
General purpose I/O pin 3.
It is programmable to transfer parallel IRQ input to serial IRQ,
Enable by KBEN# power-on setting.
General purpose I/O pin 4.
Power LED output, the signal is at low state after system reset.
VDD3v
General purpose I/O pin 5.
Parallel Interrupt Requested Input 8. This interrupt request is used
for specific RTC functions. Enable by RTCEN# power-on setting.
VDD3v
General purpose I/O pin 6.
Decode address 70h and 71h to generate chip selected signal.
Enable by RTCEN# power-on setting.
VDD3v
General purpose I/O pin 7.
Decode SA [15-11] all are at “0” state initially and setting by CR04
Bit 6.
VDD3v 14.318 MHz Clock Input.
VDD3v 14.318 MHz Buffer Output 1.
28 14MOUT 2
GP20
29
PLED
O₂₀
VDD3v 14.318 MHz Buffer Output 2.
I/O_24ts
(5V-tolerance)
General purpose I/O pin.
VDD3v
Power LED output, the signal is at low state after system reset.
F85226
9
July, 2007
V0.25P