F85226 Datasheet, PDF (28/44 Pages) Feature Integration Technology Inc. – LPC to ISA Bridge

Fintek
Feature Integration Technology Inc.
F85226
8.16 GPIO2 Input Register – Index 1Ah
Power-on default [7:0] =0000_ppppb (p: mean pin status)
Bit
Name
R/W PWR
Description
7-4 Reserved
R/W VDD3V Reserved
3 GP23_ ST
R/W VDD3V This bit is read only, when read back is the status of the pin GP23.
2 GP22_ ST
R/W VDD3V This bit is read only, when read back is the status of the pin GP22.
1 GP21_ ST
R/W VDD3V This bit is read only, when read back is the status of the pin GP21.
0 GP20_ ST
R/W VDD3V This bit is read only, when read back is the status of the pin GP20.
8.17 LED & IRQIN Control Register – Index 1Bh
Power-on default [7:0] =0000_0000b
Bit
Name
R/W PWR
Description
7 ADDR_DEC_TY R/W VDD3V If set to 1, the address decode 4 (CR34, CR35) will decode the memory cycle, else
PE[1]
it will decode io cycle.
6 ADDR_DEC_TY R/W VDD3V If set to 1, the address decode 3 (CR31, CR32) will decode the memory cycle, else
PE[0]
it will decode io cycle.
5-4 LED_FREQ
R/W VDD3V When pin GP14 or GP20 be selected to LED mode, user can use these two bits to
define LED frequency:
00: Power LED pin is tri-stated.
01: Power LED pin is driven low.
10: Power LED pin is a 1Hz toggle pulse with 50 duty cycle.
11: Power LED pin is a 1/2 Hz toggle pulse with 50 duty cycle.
3-0 IRQIN_SEL
R/W VDD3V These bits select IRQ resource for IRQIN. Four bits transfer the decimal value
to octal system.
For example:
Bit [3..0] = 1001b = 0x9h means IRQ 9 be selected.
Bit [3..0] = 1100b = 0xCh means IRQ12 be selected.
8.18 Master Setting Register – Index 1Ch
Power-on default [7:0] =1110_0001b
Bit
Name
R/W PWR
7-0 EN_MASTER16_CH R/W VDD3V Reserved
Description
F85226
23
July, 2007
V0.25P